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IRDC3843A
SupIRBuck
DESCRIPTION
TM
USER GUIDE FOR IR3843A EVALUATION BOARD
Double Sided PCB
The IR3843A is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 5mmx6mm Power QFN package. Key features offered by the IR3843A include programmable soft-start ramp, precision 0.7V reference voltage, Power Good, thermal protection, programmable switching frequency, Sequence input, Enable input, input under-voltage lockout for proper startup, and pre-bias start-up.
An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. This user guide contains the schematic and bill of materials for the IR3843A evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3843A is available in the IR3843A data sheet.
BOARD FEATURES * Vin = +12V (13.2V Max) * Vcc=+5V (5.5V Max) * Vout = +1.8V @ 0- 3A * Fs=600kHz * L= 2.2uH * Cin= 1x10uF (ceramic 1206) * Cout= 3x22uF (ceramic 0805)
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IRDC3843A
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 3A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IR3843A has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate supplies should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be connected to Vcc+ and Vcc-.
Table I. Connections
Connection VIN+ VINVcc+ VccVOUTVOUT+ Enable Seq. PGood Signal Name Vin (+12V) Ground of Vin Vcc input Ground for Vcc input Ground of Vout Vout (+1.8V) Enable Sequence Input Power Good Signal
LAYOUT
The PCB is a 4-layer board. All of layers are 2 Oz. copper. It is a double sided board with components mounted on both sides. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3843A. The feedback resistors are connected to the output voltage at the point of regulation and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path.
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IRDC3843A
Connection Diagram
Vin
GND
Enable Seq AGND PGood SS Vcc GND Vo GND TOP SIDE
BOTTOM SIDE
Fig. 1: Connection diagram of IR384xA evaluation boards
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IRDC3843A
Fig. 2: Board layout, top overlay
Fig. 3: Board layout, bottom overlay (rear view)
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Fig. 4: Board layout, mid-layer I.
Fig. 5: Board layout, mid-layer II.
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1
1
14
2.74K 1 Boot seq Vin 12 FB COMP AGnd1 L1 2.2uH PGnd 10 Rt SS Vcc OCset 9 8 15 VCC C13 1uF R12 2.26K Enable 2 GND 3 4 SW 5 SS 6 PGood AGnd2 7 R9 23.7K C10 0.1uF VCC 1 1
8.2nF
U1
13
1
1
1
1
4.99K R3 3.16k
20 A
B
IRDC3843A
Fig. 6: Schematic of the IR3843A evaluation board
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Enable Vin (+12V) R18 1 49.9K C7 0.1uF C3 N/S C2 10uF Vin1 R16 0 R19 7.5K Vin+ VCC
Seq.
Ceramic cap 16V 10uF 1206
R20 C11 C24 180pF R1 C26 0.1uF
N/S
Vout (+1.8V) Vout+ 1 C16 C18 N/S C17 22uF 22uF C15 22uF C14 0.1uF Vout1
IR3843A
11
Vcc-
Vcc+
PGood
R17 10.0K
R4 130 2200pF R2
C8
R6
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IRDC3843A
Bill of Materials
Ite m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Quantit y 1 4 1 1 1 3 Part Reference C2 C7 C14 C24 C10 C8 C11 C13 C15 C16 C17 C3,C18 C26 L1 R1 R2 R3 R4 R6 R9 R16 R12 R17 R18 R19 R20 U1 Value 10uF 0.1uF 2200pF 180pF 1uF 22uF Not used 8200pF 2.2uH 2.74k 4.99k 3.16k 130 20 23.7K 0 2.26K 10K 49.9k 7.5k Not used IR3843A
3A SupIRBuck, PQFN 5x6mm
Description 10uF,1206,16V, X7R, 20% 0603, 25V, X7R, 10% 0603,50V,X7R, 10% 50V, 0603, NP0, 5% 16V, 0603, X5R, 10% 0805, 6.3V, X5R, 20%
Manufacturer Panasonic - ECG Panasonic Panasonic Murata Murata Panasonic
Part Number ECJ-3YX1C106K ECJ-1VB1E104K ECJ-1VB1H222K GRM1885C1H181JA01D GRM188R61C105KA93B ECJ-2FB0J226M
0603, 50V, X7R, 10%
7.05*6.6*4.8mm,12.5m max
Panasonic Cyntec Rohm Rohm Rohm Panasonic Vishay/Dale Rohm Vishay/Dale Rohm Rohm Rohm Rohm
ECJ-1VB1H822K PCMB065T-2R2MS MCR03EZPFX2741 MCR03EZPFX4991 MCR03EZPFX3161 ERJ-3EKF1300V CRCW060320R0FKEA MCR03EZPFX2372 CRCW06030000Z0EA MCR03EZPFX2261 MCR03EZPFX1002 MCR03EZPFX4992 MCR03EZPFX7501
0603,1/10W,1% 0603,1/10W,1% 0603,1/10W,1% 0603,1/10W,1% 0603,1/10 W,1% 0603,1/10W,1% 0603,1/10 W,5% 0603,1/10 W,1% 0603,1/10 W,1% 0603,1/10 W,1% 0603,1/10W,1%
International Rectifier
IR3843AMPbF
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IRDC3843A
TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-3A, Room Temperature, No Air Flow
Fig. 7. Start up at 3A Load Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable
Fig. 8. Start up at 3A Load, Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood
Fig. 9. Start up with 1.62V Pre Bias, 0A Load, Ch2:Vo, Ch3:VSS
Fig. 10. Output Voltage Ripple, 3A load Ch2: Vo
Fig. 11. Inductor node at 3A load Ch1:LX
Fig. 12. Short (Hiccup) Recovery Ch2:Vo , Ch3:VSS
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IRDC3843A
TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0-3A, Room Temperature, No Air Flow
Fig. 13. Transient Response, 1.5A to 3A step 2.5A/s Ch2:Vo
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IRDC3843A
TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=3A, Room Temperature, No Air Flow
Fig. 14. Bode Plot at 3A load shows a bandwidth of 83.8KHz and phase margin of 59.8
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IRDC3843A
TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0- 3A, Room Temperature, No Air Flow
IR3843A 92
90
88 Efficiency(%)
86
84
82
80
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
Iout(A)
Fig.15: Efficiency versus load current
IR3843A 0.700 0.600 0.500 0.400 0.300 0.200 0.100 0.000 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Iout(A)
Power Dissipation(W)
Fig.16: Power loss versus load current
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IRDC3843A
THERMAL IMAGE Vin=12V, Vcc=5V, Vo=1.8V, Io=3A, Room Temperature, No Air Flow
Fig. 17: Thermal Image at 3A load Test points 1 and 2 are IR3843A and inductor, respectively.
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IRDC3843A
PCB Metal and Components Placement
Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper.
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IRDC3843A
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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IRDC3843A
Stencil Design
* The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
*
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IRDC3843A
BOTTOM VIEW
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (320) 252-7105 TAC Fax: (320) 252-7903 This product has been designed and qualified for the Consumer market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 01/10
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